Field of the Invention
The invention relates to a circuit configuration for compensating runtime and pulse-duty-factor differences of two input signals of approximately equal frequency and phase, whereby for each input signal respectively present at an input of the circuit configuration, a signal path is provided that, dependent on the state of the output, is influenced in such a way that the output signal follows the input signal that changes first.
In integrated semiconductor circuits, in particular memory circuits, the problem arises that in particular clock signals must be distributed to a plurality of sections of the semiconductor circuit, for example to a plurality of memory banks of an integrated memory circuit. In what is known as a clock distribution tree, runtime and pulse-duty-factor differences between the distributed signals can thereby arise, above all through the driver stage, as well as through the respective load.
FIG. 1 shows a prior art circuit configuration previously used for compensating runtime and pulse-duty-factor errors between two input signals. That circuit configuration has in principle two signal paths that are enabled or blocked in dependence on the state of the outputs. Each signal path respectively comprises a JK flip-flop 20, 30 and logic elements 21, 22, 23 and 31, 32 and 33. The output states at the Q outputs of JK flip-flops 20 and 30 are respectively supplied to a J- and to a K- input of an additional JK flip-flop 40, whose Q output forms an output terminal OUT of the circuit configuration. the output states of the JK flip-flop 40 are fed back to reset terminals R of the JK flip-flops 20 and 30 of the two signal paths. In this way, the signal paths are enabled or blocked, dependent on the output state of the JK flip-flop 40.
The circuit configuration shown in FIG. 1 realizes the following truth table:
Here, OUTT indicates the previous output state of JK flip-flop 40.
Disadvantages of the previously standard circuit configuration shown in FIG. 1 are the relatively high circuit outlay, the relatively large chip surface occupied by the circuit, and the long runtime of the circuit configuration itself.
The object of the present invention is to provide a circuit configuration which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which provides for a simplified circuit configuration that realizes the above truth table, and whose output follows the first-changing input signal, and in which the occurrence of transverse current is prevented.
With the above and other objects in view there is provided, in accordance with the invention, a circuit configuration for compensating runtime and pulse-duty-factor differences of two input signals having substantially equal frequency and phase, which comprises:
a first input receiving a first input signal;
a second input receiving a second input signal;
an output for outputting an output signal;
a first signal path from the first input to the output and a second signal path from the second input to the output, wherein the signal path is influenced such that the output signal follows a first-changing input signal; and
a time-delay element connected between the output and the first and second inputs, for a delayed feedback of the output signal, wherein a delay time of the time delay element is such that the first and second inputs are prepared for a next change of the input signal, and the delay time is greater than a maximum chronological deviation between the first and second input signals.
In accordance with an added feature of the invention, the output signal depends on the first and second input signals in accordance with the following truth table:
whereby OUTT indicates a previous state of the output signal OUT.
In accordance with an additional feature of the invention, the maximum chronological deviation between the first and second input signals is predetermined by a process selected from the group consisting of measurement, simulation, and estimation, and the time-delay element is configured for adjusting the delay time.
With the above and other objects in view there is also provided, in accordance with the invention, an integrated semiconductor circuit which comprises a clock distribution tree for distributing a clock signal to a plurality of circuit sections, and at least one circuit configuration according to the above-summarized invention, for compensating runtime and pulse-duty-factor errors of the distributed clock signal.
The integrated semiconductor circuit is a memory circuit in a preferred embodiment, and the circuit sections are memory banks.
In other words, it is a basic premise of the novel circuit configuration to comprise a time-delay element for the delayed feeding back of its output signal to its inputs, in such a way that the inputs are prepared for the next change of signal.
The condition must thereby be maintained that the delay time of the time-delay element is greater than the maximum chronological deviation between the two input signals.
This means that for the correct functioning of the inventive circuit configuration the maximum chronological deviation between the two input signals must be known. It can for example be determined by measurement, and the delay time of the time-delay element can be set, through corresponding adjustment means, greater than the measured maximum chronological deviation between the two input signals.
A circuit configuration of this type can be used with particular advantage in integrated semiconductor circuits, in particular memory circuits.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.